- E-Mail:
- wmueller@hni.uni-paderborn.de
- Phone:
- +49 5251 60-6352
- Web:
- Homepage
- Office Address:
-
Fürstenallee 11
33102 Paderborn - Room:
- F0.431
Research
Publications
Latest Publications
Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study
K.A. Hannemann, H.B. Bütün, W. Müller, J.C. Scheytt, in: MBMV 2025 - 28. 365体育_足球比分网￥投注直播官网 Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen, VDE Verlag, Warnemünde, 2025.
Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells
L. Luchterhandt, V. Govindasamy, Y. Wang, R. D?mer, W. Müller, J.C. Scheytt, in: OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits, Lyon, France, 2025.
60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design
B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025).
A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology
M. Iftekhar, B. Sadiye, W. Müller, J.C. Scheytt, in: IEEE Nordic Circuits and Systems Conference (NORCAS), 2025.
A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing
P. Palomero Bernardo, P. Schmid, O. Bringmann, M. Iftekhar, B. Sadiye, W. Müller, A. Koch, E. Jentsch, A. Sauer, I. Feldner, W. Ecker, in: DATE 24 - Design Automation and Test in Europe, 2024.
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Teaching
Current Courses
- Topics in Systems Engineering - IC Design
- Projekt Angewandte Programmierung
- Grundlagen des VLSI-Entwurfs